Sum modulo ten accumulator



April 1962 A. c. REYNOLDS, JR 3,030,020

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SUM MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18 Sheets-Sheet2 April 17, 1962 A. c. REYNOLDS, JR 3,030,020

sum MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18 Sheets-Sheet3 H FIG a BIT AND ATTORNEY April 1962 A. c. REYNOLDS, JR 3,030,020

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suM MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18 Sheets-Sheet5 FIG. /7

CORRECTION IN k K COMPLETED ERROR n an i STORE N l CHECK TIME READ PULSElNl/EN TOR By A. C. REYNOLDS JR ATTORNEY April 1962 A. c. REYNOLDS, JR3,030,020

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ATTORNEY April 1962 A. 'c. REYNOLDS, JR 3,030,020

' SUM MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18Sheets$he'et 12 OUNTER SELECTION c PULSES 26 BIT m E CCT. 77 F w FOURWIRE BIT TRUNK 76 l lNl/ENTOR A. C. REYNOLDS JR.

A T TORNE V APT-i1 1962 A. c. REYNOLDS, JR 3,030,020

SUM MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18 Sheets-Sheet15 FIG. 27

OUTPUT BITS EXTENTED TO F|G.3l

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ATTORNEY A ril 17, 1962 A. c. REYNOLDS, JR 3,030,020

SUM MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18 Sheets-Sheet14 lNl/ENTOR B A. C REYNOLDS JR.

ATTOPNEV April 1962 A. c. REYNOLDS, JR 3,030,020

SUM MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18 Sheets-Sheet15 A T TORNE Y April 1962 A. c. REYNOLDS, JR 3,030,020

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sum MODULO TEN ACCUMULATOR Original Filed Feb. 26, 1957 18 Sheets-Sheet18 United States Patent 3,030,020 SUM MODU EN A UMULAT Andrew CraigReynolds, Jr., Waterbury, Conn., assignor This is a division ofapplication Serial -Number 642,509, now Patent No. 2,969,912, filedFebruary 26, 1957, for improvements in Error Detecting and CorrectingCircuits.

This invention relates to means for detecting and correcting errors intransmitted information and relates particularly to electronicregistering means for receiving, accumulating and storing the codedmanifestations of decimal digits.

An object of the invention is to provide supervisory means for examiningcoded items of information, each accompanied by its unique checkingitems, and to delay the further processing movement thereof until adetected error can be corrected or until an alarm may be given throughdisabling means provided to report a non-correctable error. i

The invention consists in general of a means for handling information intransit. Each item of information, which, by way of example, may be aten digit number before entry into a processing machine, has certaincheck digits derived therefrom and these check digits are thereafterassociated With this ten digit number and become par-t of the word. Onegroup of these check digits consists of the decimal equivalent of thebinary number formed by the selection of one of two distinguishablecharacteristics from each of the binary code representations of each oithe decimal digits of the said ten digit number.

For purposes of explanation an example will be discussed in great detailthroughout this specification. 'It will be assumed that the decimalnumber the least significant 'bit of each group, thus producing thebinary number which, translated into its decimal equivalent, becomes andwhich, expressed in the binary decimal notation (for purposes which willappear hereinafter), becomes Another unique check digit is derived byusing the units digit .of the sum of the digits of the said'number, thisbeing known as the sum modulo of the number. The sum-of so that thedigit 4.is a derived checkdigit which along with the number 0754 isassociated with the said number and which accompanies the said number inits movements rs eh h rr e ns mash n Thi te of in or 3,030,020 PatentedApr. 17, 1962 ice tion is precalculated so that when the number and itscheck digits are moved about they appear as an this is xp essed n the bna y de ma ode so t a it forms a uc e s n of fi t en tou p e cod s wh chmay be tr nsmitted ove a on nt on l our i i t un l will b a med t a thmea for s ssive y en ering and tr smit g e c of t es c de er suc a :fourWir bi t unk in which he bits re sim l n sly moved is entirelyconventional,

The invention consists of means for successively gating these fifteendigits into fifteen digit stores for processing whi h compri e twoprincipal opera i ns. First the tour cheek digits 0754 are t anslatedinto an equivalent binary numbe and this is compared with the ten digitnumber which has actually been stored. Let us assume that in processingand by reason of some random error, the second digit 6 has become a 7.The comparison'would then be between and it will at once be apparentthat there is an error'in the second place.

At the same time and during the entry of the ten digits of this word,these ten digits are summed step by step and the sum of the digits ofthe number containing the error comes out to be 45 so that the summodulo 10, which is 5, fails to comparewith the last (fifteenth place)check digit 4.

These two check failures then immediately start a correcting operation.This consists of opening a gate to the second place digit store and theintroduction thereinto of a train of correcting pulses andsimultaneously therewith the introduction into the means for summing thedigits of exactly the same number of pulses. This has the effect ofadvancing the record in the second place ,digit store successivelythrough the valuesS, 9., 0, 1, 2, 3, 4,5 ,and 6-and simultaneouslytherewith of advancing the record in the summing device successivelythrough the values 46, 47, 48, 49, 50, 51, 52, 53 and 54. When the lastvalue 54 is reached, its units ,value 4 will compare exactly with thelast place check digit and this will bring about a circuit changeconstituting a satisfaction signal which will stop further correctionoperations and will cause the corrected ten digit number to betransferred to a use circuit, such as an arithmetic section of acomputer.

It should be noted that if no error had been detected the said ten digititem of information would have been immediately passed along to the saiduse circuit.

From-the above discussion, and further by way of .example, it willappear that with circuits and apparatus hereinabove set forth, an errorcan be detected only if it appears in the 1 bit place of some one of thedigits form- -ing-the ten digit word, for otherwise the four digit check0754 would remain the same while only the sum modulo 10 check digitwould change. Since under these conditions therewould be an absence ofinformation necessary for the operation of the proper gate to the storecontaining the digit in error,'this will be known as a noncorrectableerror and can only result in an alarm.

It may also be noted that where the four digit check number shows adeviation but the sum modulo 10 check digit shows no deviation, thisalso constitutes a non-correctable error for no information exists whichwill control the number of correction pulses which must be in troducedinto the store .or stores containing an erroneous number. Where morethan one erroneous decimal digit exists in store then a non-correctableerror will be reported, for while the four digit check may lead to thediscovery of the location of such multiple errors, the'single digit summodulo check digit cannot report the differing magnitude of two or moreerrors.

While the system outlined above is particularly useful for the detectionand correction of errors occurring in the transmission of data in pulseform, e.g. transmission of 'a number of pulses in seriatim correspondingto the value of a digit as in the telephone dial system, it is to beunderstood that the present invention contemplates means for detectingand correcting errors occurring in data transmitted in any digital form.

When transmitting the representation of a digit by a number of pulsescorresponding to the value of a digit, an error changing the transmittedvalue by more than .one is far less likely than an error changing thetransmitted value by one. For example, when transmitting the digit byseven pulses in seriatim, it is far less likely that more than 8 or lessthan 6 pulses will be received than that 8 or 6 pulses will be received,the former constituting a double error While the latter constitutes asingle error. The system outlined above is quite accurate for datatransmitted in pulse form. This data, of

course, may be subsequently translated into the binary coded decimalform or into any other coded form. If, however, the transmission is overfour parallel wires in the binary coded decimal form, for example, thenthe check 7 digits would be derived from parity or redundant bits inthis manner would thus be which binary number translates into thedecimal number This number with the modulo 10 sum of the digits, 4, isnow used in the same manner as explained above, and is transmitted as Itis to be noted that, in both the above examples, two mutually exclusivecharacteristics of each digit have been chosen as the basis for formingthe binary check number, in the first case the odd or-evencharacteristic of the decimal number and in the second case the odd oreven characteristic of the sum of the bits used in the binary coded formof such decimal number.

The binary check number, so formed has been translated into the decimalsystem of notation for transmission with the information carryingdigits. his to be noted further that the invention is not limited to thedecimal system of notation since, the binary check number can betranslated into any system of notation as desired, for example, base 36or larger for handling both alphabetic and numeric data.

It is further to be noted that in the first example given a singlerandom error in the 1 bit place may be specifically detected andcorrected when the odd or even value of a decimal digit is thecharacteristic used as a control.

Experience with the transmission of information particularly in greatdigital information handling networks such as the telephone system andthe digital computers has shown that the occurrence of such singlerandom errors is extremely rare and that the occurrence of a doubleerror 'is so extraordinarily rare that provision for its detection isalmost never made. rection of an error in the 1 bit place alone willdetect However, the detection and coronly 25% of the random errors forwhich it is believed provision should be made for it is just as likelythat a random error may occur in the 2 bit, the 4 bit, or the 8 bitplace as it is that such an error may occur in the 1 bit place.

A feature of the invention therefore is a means for detecting andcorrecting a single error which may occur at random in any one of thefour places of the binary Although this last number translates to thedecimal number 0796, this translation is immaterial since it is thecomparison of these two ten place binary numbers which is used to locatethe error and since in the comparison circuits inequality appears in thesecond place (the 256 bit place) it is this digit as recorded at thedistant end that must be corrected.

From a practical standpoint the code 0010 is equivalent to the decimalvalue 2. This changes the sum of the bits from even to odd and pointsout the location of an error as being in the second digital place. Thiswill require the transmission of 4 correcting pulses to advance theregister from 0010 through the value 0011 to the correct value 0110. Theerroneous code 0010 which is transmitted being equal to the decimalvalue 2, will cause the sum of the decimal digits to be 40 instead ofthe proper sum 44, so that as the 4 correcting pulses are transmitted tothe second place register, they also advance the modulo 10 summingdevice from the value 40 through the value the transmission of 2correcting pulses to advance the second place register from the value0100 successively through the value 0101 to 0110. Since the coderepresents the decimal value 4, the sum of the digits calculated on thereceipt of these codes will turn out to be 42 showing the sum modulo tenequal to 2 and since this does not compare to the digit 4 transmitted,these two correcting pulses will also run the modulo 10 summing devicesuccessively through the value 43 until it reaches the value 44 toexhibit the value 4 which compares with the magnitude check digit.

Again, let it be assumed that by random error, the code 0110 is sent as0111. In this case, the sum of the bits has been changed from even toodd, The four digit location code reports an error in the second placeand 1 the modulo ten device reports a sum of 45 or a value 5 instead ofthe value 4 carried by the magnitude code.

In this case nine correction pulses will be transmitted to run thesecond place register from the value 0111 successively through thevalues 1000, 1001, 0000, 0001, 0010, 0011, 0100, 0101 until it reachesthe value 0110, the

V modulo 10 summing device advancing simultaneously

